A High-Level Modeling System (HLMS) refers to a computer-based circuit design tool that allows circuit designers to create circuits at a high level of abstraction. Typically, an HLMS provides a graphic design environment within which circuit designers can create circuit designs using a “drag-and-drop” design paradigm. A circuit designer can drag graphic blocks, where each graphic block represents a particular circuit function, into the design environment. For example, each graphic block can represent a function such as multiplexing, addition, multiplication, filtering, or the like. Within the design environment, the circuit designer also can specify connectivity among the graphic blocks, e.g., draw links, to indicate connectivity and signal flows within the circuit design.
One example of an HLMS is the Xilinx System Generator for Digital Signal Processing (DSP), also known as “SysGen.” SysGen is a high-performance, computer-based design tool that executes as part of Simulink to provide a high-level, graphical modeling environment. Simulink runs in Matlab from The Math Works, Inc., of Natick, Mass. and is an interactive tool for modeling, simulating, and analyzing dynamical systems.
When a circuit designer creates a module as part of a new circuit design, the circuit designer must specify that module using a hardware description language (HDL). Aspects of the module, such as the interface, must be specified manually. The interface of the module must match the interface of each other module of the circuit design to which the newly created module is coupled. Specifying the interface of a module, being manual in nature, is often an error prone and tedious task. Several revisions of the interface may be required before the newly created module compiles correctly and, therefore, can be integrated into the circuit design and represented within the HLMS.